There is proposed a memory device having a three-dimensional structure. In this memory device, a memory hole is formed in a stacked body in which a plurality of electrode layers functioning as control gates in memory cells are alternately stacked with insulating layers. A silicon body constituting a channel is provided via a charge storage film on the sidewall of the memory hole. As an extraction contact structure of the electrode layers, there is proposed a structure in which a plug is connected to each of the plurality of electrode layers processed into a staircase structure.
In the staircase structure section, each electrode layer is once connected with the upper-layer interconnection through the plug extending upward from the electrode layer. Furthermore, the upper-layer interconnection is routed to the outside of the staircase structure section. Then, the upper-layer interconnection is connected to a circuit interconnection formed on the substrate surface through another plug extending from the upper-layer interconnection toward the substrate side. Such an extraction structure of interconnection may hamper the reduction of the chip area.